发明名称 STACK TYPE SEMICONDUCTOR PACKAGE
摘要 PURPOSE: A stacked semiconductor package is provided to accomplish the miniaturization of a package product by manufacturing without securing the clearance height of a molding unit in an upper region. CONSTITUTION: A first semiconductor chip(121) is laminated on a first substrate(111) to multi-stage. A second semiconductor chip(131) is laminated on a second substrate(112) to multi-stage. A first conductive wire(140) electrically interlinks a first bonding pad(122) and a connection pad of the first substrate. A second conductive wire(150) electrically interlinks a connection pad of the second substrate and a second bonding pad(132). A junction unit(190) laminates and welds first and second lamination by having a connection bonding layer of a constant thickness.
申请公布号 KR20110124063(A) 申请公布日期 2011.11.16
申请号 KR20100043637 申请日期 2010.05.10
申请人 HANA MICRON CO., LTD. 发明人 HWANG, CHUL KYU;LEE, HYUN WOO
分类号 H01L23/12 主分类号 H01L23/12
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