| 摘要 |
A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Each of a number of conductive features within a gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature having a centerline aligned parallel to a first direction. The conductive features respectively form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. Gate electrodes of the first PMOS and second NMOS transistor devices are electrically connected in part by a first conductor within a first interconnect level. Gate electrodes of the second PMOS and first NMOS transistor devices are electrically connected in part by a second conductor within the first interconnect level. The first PMOS, second PMOS, first NMOS, and second NMOS transistor devices define a cross-coupled transistor configuration having commonly oriented gate electrodes.
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