发明名称 |
VERZÖGERUNGSREGELSCHLEIFE |
摘要 |
The delay-locked-loop (100) comprises at least two delay elements, of which a first delay element (10) has a positive delay line and an input for receiving a clock, and of which a second delay element (11) has a negative delay line and an input for receiving a clock, a clock selector (13) for selecting the clock from one of the two delay lines, a phase detector (14) with an input for receiving data and for comparing the phase of the data to that of the selected clock, and a control block (12) which produces control signals for controlling the two delay lines such that they react in opposite directions to a signal from the phase detector (14). Such a delay-locked-loop suitable for accurate clock generation in plesio-sinchronous communication systems. |
申请公布号 |
AT532267(T) |
申请公布日期 |
2011.11.15 |
申请号 |
AT20060780203T |
申请日期 |
2006.07.25 |
申请人 |
KONINKLIJKE PHILIPS ELECTRONICS N.V. |
发明人 |
PETKOV, PAVEL;CONDER, JIM;GERFERS, FRIEDEL |
分类号 |
H03L7/081 |
主分类号 |
H03L7/081 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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