SRAM CELL

摘要

PURPOSE: An SRAM cell is provided to reduce remarkably operation consumption power by forming a memory cell with four MOS transistors. CONSTITUTION: In an SRAM cell, a first PMOS transistor(MP1) is connected to a first bit line(BL). The source of the first NMOS transistor(MN1) is connected to a first word line(WL W). The drain of the first NMOS transistor is connected to the drain of a first PMOS transistor. The gate of the first NMOS transistor is connected to the gate of the first PMOS transistor. A second PMOS transistor(MP2) has a source connected to a second bit line(/BL). The source of the second NMOS transistor(MN2) is connected to a second word line. The drain of the second NMOS transistor is connected to the drain of the second PMOS transistor. The gate of the second NMOS transistor is connected to the gate of the second PMOS transistor.