SYSTEM AND METHOD TO REDUCE LEAKAGE CURRENT BY A COMMON POTENTIAL ON READ BIT LINE AND READ WORD LINE DURING NON-READ OPERATIONS

摘要

A system and method to manage leakage of a complementary metal - oxide - semiconductor (CMOS) read transistor in a memory cell (200). In a particular embodiment, a memory cell is disclosed that includes a storage element (104) and a complementary metal - oxide - semiconductor (CMOS) read transisto (106) r. The CMOS read transistor includes a first terminal coupled to a read word line (RWL), a second terminal coupled to a read bit line(RBL), and a third terminal coupled to the storage element (104). During a non-read operating time, the read word line and the read bit line are both maintained at substantially the same voltage level. During a read operation, the read word line is maintained at a particular voltage level until after a voltage representing data stored at the storage element is sensed by the CMOS read transistor.