| 摘要 |
An integrated circuit design apparatus is provided with a power supply voltage variation analysis tool calculating variations of power supply voltages of respective instances integrated within a target circuit; a determination module comparing the variations of the power supply voltages with first and second reference levels, the second reference level being smaller than the first reference level; a redesign module adapted to redesign the target circuit when at least one of the variations of the power supply voltages is larger than the first reference level; a delay variation calculation module adapted to correct circuit delay data of the respective instances based on the variations of the power supply voltages of the respective instances; a static timing analysis tool performing timing verification of the target integrated circuit. The timing verification in connection with each of the instances is performed based on the corrected circuit delay data, when a variation of a power supply voltage of the each of the instances is in a range from the second reference level to the first reference level, and performed based on the circuit delay data uncorrected, when the variation of the power supply voltage of the each of the instances is smaller than the second reference level.
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