发明名称 Synchronous circuit and method for receiving data
摘要 The present invention includes: a synchronous-word detecting unit receives a baseband received signal including a synchronous word and data for each frame, and detects whether or not the synchronous word is coincided with an expected value in the baseband received signal by using an N-(N is an integer of 2 or larger) phase sampling clock; a phase information retaining unit retains phase information accumulatively including results detected for a plurality of frames by the synchronous-word detecting unit, and determines a phase to be sampled on the basis of the retained phase information; a phase selecting unit selects and determines a phase of the sampling clock on the basis of determination by the phase information retaining unit; and a FIFO buffer samples the data from the baseband received signal, and outputs the sampled data.
申请公布号 US8054927(B2) 申请公布日期 2011.11.08
申请号 US20080219522 申请日期 2008.07.23
申请人 RENESAS ELECTRONICS CORPORATION 发明人 KONISHI SHINYA
分类号 H04L7/00 主分类号 H04L7/00
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