发明名称 |
SERIALLY CONNECTED MEMORY HAVING SUBDIVIDED DATA INTERFACE |
摘要 |
<p>A memory system has a controller. A plurality of memory devices are serially interconnected with the controller via an n-bit data interface. The memory system is configurable in a first mode to communicate each read and write operation between the controller and the memory devices using all n bits of the data interface. The memory system is configurable in a second mode to concurrently: communicate data associated with a first operation between the controller and a first target memory device using only m bits of the data interface, where m is less than n; and communicate data associated with a second operation between the controller and a second target memory device using the remaining n-m bits of the data interface. A memory device, a memory controller, and a method are also described.</p> |
申请公布号 |
WO2011134051(A1) |
申请公布日期 |
2011.11.03 |
申请号 |
WO2011CA00468 |
申请日期 |
2011.04.26 |
申请人 |
SCHUETZ, ROLAND;MOSAID TECHNOLOGIES INCORPORATED |
发明人 |
SCHUETZ, ROLAND |
分类号 |
G11C7/10;G11C5/02;G11C11/4093 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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