| 摘要 |
An system for enhancing the security of a logic device by preventing attacks that utilise observable features such as the power supply or electromagnetic radiation, so called, "side-channel attacks". Specifically, the present invention comprises a technique and method for reducing ability to monitor the relationship between currents in the system and the data in the system by closing the overall clock eye diagram, whilst keeping the eye diagram for connected stages open. The degree of eye closure for connected pipeline stages allows the system to run closer to its maximum operating speed compared to the use of system wide clock jitter, yet the overall closure provides security that is absent from systems with a partially open eye. The system uses multiple clock signals (391-394) which are delayed with respect to each other and operate on D type flip flops (410, 430, 490) either side of logic elements in the device (420, 440).
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