发明名称 CHIP PACKAGE
摘要 A quad flat non-leaded package including a first patterned conductive layer, a second patterned conductive layer, a chip, bonding wires and a molding compound is provided. The first patterned conductive layer defines a first space, and the second patterned conductive layer defines a second space, wherein the first space overlaps the second space and a part of the second patterned conductive layer surrounding the second space. The chip is disposed on the second patterned conductive layer. The bonding wires are connected between the chip and the second patterned conductive layer. The molding compound encapsulates the second patterned conductive layers, the chip and the bonding wires. In addition, a method of manufacturing a quad flat non-leaded package is also provided.
申请公布号 US2011260327(A1) 申请公布日期 2011.10.27
申请号 US201113173255 申请日期 2011.06.30
申请人 ADVANCED SEMICONDUCTOR ENGINEERING, INC. 发明人 LEE MING-CHIANG
分类号 H01L23/48 主分类号 H01L23/48
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