| 摘要 |
PROBLEM TO BE SOLVED: To simplify the configuration of an encoding circuit while securing a required parallelism.SOLUTION: Information bits are input to the encoding circuit 51 at (q) bit units at every 1 clock cycle. In an input parallel conversion circuit 62, the information bits input at the (q) bit units are stored in a buffer, and the information bits in mp bit parts are output in the stored order in the stored information bits at the timing of excesses over mp bits of the quantities of storages. In a parity generation circuit 63, parity bits are generated on the basis of the information bits input at mp bit units, and output at (q) bit units. In a multiplexer 64, the parity bits are added to the information bits delayed in a delay circuit 61 and code bits are generated. This invention can apply to a device conducting an LDPC encoding. |
