| 摘要 |
PROBLEM TO BE SOLVED: To provide a reconfigurable circuit absorbing latency of calculation execution by a simple circuit configuration.SOLUTION: This reconfigurable circuit includes: a data calculation part including a plurality of calculation units, each of which performs calculation to a plurality of data when all of the plurality of data simultaneously come into a valid state, and continuously outputs valid-state data indicative of a calculation result obtained by the calculation while all the plurality of data are in the valid state; a data selection part configured to connect the calculation units to one another in a reconfigurable manner; and a data input part configured to hold, as input data, data input to the series of calculation units connected by the data selection part to perform a series of calculations. Valid and invalid states of data are represented by signals accompanying the data as a pair and indicative of validity and invalidity, and the input data supplied from the data input part to the data calculation part are fixed to valid-state identical data while the series of calculations are performed. |
