| 摘要 |
A processor 4 is provided with an instruction decoder 32 responsive to prefetch instructions which trigger pre-load operations, such as page table walks and cache line fetches. The instruction decoder identifies if the memory address associated with the preload instruction matches a null value and suppresses the preload operation if the memory address does match the null value. The null value may be set under program control, it may be predetermined as a fixed value (e.g. zero), a range of values, or may be set under hardware control, such as corresponding to memory addresses of a page identified by a memory management unit as non-accessible. The address mapping is stored by means of a translation lookaside buffer 20. |
