发明名称 |
Buffering deserialized pixel data in a graphics processor unit pipeline |
摘要 |
An arithmetic logic stage in a graphics processor unit pipeline includes a number of arithmetic logic units (ALUs) and at least one buffer that stores pixel data for a group of pixels. Each clock cycle, the buffer stores one row of a series of rows of pixel data. A deserializer deserializes the rows of pixel data before the pixel data is placed in the buffer. After the buffer accumulates all rows of pixel data for a pixel, then the pixel data for the pixel can be operated on by the ALUs.
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申请公布号 |
US2011254848(A1) |
申请公布日期 |
2011.10.20 |
申请号 |
US20070893499 |
申请日期 |
2007.08.15 |
申请人 |
BERGLAND TYSON J;OKRUHLICA CRAIG M;HUTCHINS EDWARD A;TOKSVIG MICHAEL J M;MAHAN JUSTIN M |
发明人 |
BERGLAND TYSON J.;OKRUHLICA CRAIG M.;HUTCHINS EDWARD A.;TOKSVIG MICHAEL J.M.;MAHAN JUSTIN M. |
分类号 |
G06T1/00 |
主分类号 |
G06T1/00 |
代理机构 |
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代理人 |
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