INSTRUCTION FETCH DEVICE, PROCESSOR, PROGRAM CONVERSION DEVICE, AND PROGRAM CONVERSION METHOD

摘要

PROBLEM TO BE SOLVED: To improve throughput by averaging penalty due to next-line prefetch for instruction prefetch.SOLUTION: During execution of a cache line (current line) including an instruction to be executed, both a cache line (next line) following the above cache line and a cache line (branch destination line) including the branch destination instruction of a branch instruction included in the current line are prefetched to an instruction cache. The branch destination line is arranged to have a line address different from that of the next line in order to avoid conflict in the instruction cache. The branch instruction of the current line is arranged in the latter part of the current line in order to keep a margin until the prefetch of the both lines is completed.