发明名称 System and method for load balancing a video signal in a multi-core processor
摘要 Sequential video data frames are encoded using cores including a first core and a second core. A first beginning frame is divided into slices. The first core is assigned to process a first slice. The second core is assigned to process a second slice. The first beginning frame is processed using the cores which results in a first ending frame in which the first slice was partitioned into a third slice and a fourth slice. The third slice was processed by the first core. The fourth slice and the second slice were processed by the second core. A second beginning frame, which immediately follows the first ending frame, is divided into a second plurality of slices. The first core is assigned to the third slice. The second core is assigned to a fifth slice which has a size equal to a sum of the second and fourth slices.
申请公布号 US8041132(B2) 申请公布日期 2011.10.18
申请号 US20080147850 申请日期 2008.06.27
申请人 FREESCALE SEMICONDUCTOR, INC. 发明人 YAN YONG
分类号 G06K9/36 主分类号 G06K9/36
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