发明名称 Transmitting apparatus with bit arrangement method
摘要 <p>A transmitting apparatus comprising circuitry operable to generate a plurality of bit sequences using bits included in a first data block and a second data block, circuitry operable to control the plurality of bit sequences to correspond to a signal point on the phase plane, comprising a bit sequence generating unit operable to control the generation of the bit sequences to adjust an occupation rate occupied with predetermined bits included in the first data block (CODE BLOCK 1) to be closer to an occupation rate occupied with predetermined bits included in the second data block (CODE BLOCK 2) in regard to bit positions of the predetermined bits, based on an error tolerance of the respective bit sequences generated resulting from the correspondence to a signal point on the phase plane, and circuitry operable to transmit the signals obtained by multi-level modulations in accordance with each signal point.</p>
申请公布号 EP2375667(A1) 申请公布日期 2011.10.12
申请号 EP20100184618 申请日期 2004.10.15
申请人 FUJITSU LIMITED 发明人 YANO, TETSUYA;OBUCHI, KAZUHISA;MIYAZAKI, SHUNJI
分类号 H03M13/25;H04L27/34;H03M13/29;H04B7/216;H04J13/00;H04L1/00;H04L1/16;H04L12/66;H04L27/00 主分类号 H03M13/25
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