| 摘要 |
A semiconductor device includes a plurality of CML buffering units configured to buffer, in parallel, a plurality of serially applied data signals to CML levels in a sequence responding to multi-phase source clocks; and a CMOS amplification block configured to amplify a plurality of buffered data signals, sequentially outputted from the plurality of CML buffering units, to CMOS levels in response to the multi-phase source clocks, and output amplified data signals in parallel at the same timing.
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