发明名称 Wiring substrate with plurality of wiring and insulating layers with a solder resist layer covering a wiring layer on the outside of outer insulating layer but exposing the holes in the outer insulating layer
摘要 In a wiring substrate in which plural wiring layers and insulating layers are alternately stacked and the adjacent wiring layers are electrically connected through a via hole formed in the insulating layer, plural holes constructing substrate management information recognizable as a character, a symbol, etc. are formed in the outside insulating layer of the insulating layers.
申请公布号 US8035033(B2) 申请公布日期 2011.10.11
申请号 US20090372158 申请日期 2009.02.17
申请人 SHINKO ELECTRIC INDUSTRIES CO., LTD. 发明人 KOBAYASHI KAZUTAKA
分类号 H05K1/00 主分类号 H05K1/00
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