发明名称 DELAY CIRCUIT FOR PLC TYPE DEMODULATION
摘要 <p>Disclosed is a delay circuit which is for PLC type demodulation and which is not easily affected by the positional dependence of the polarisation conversion efficiency of a wavelength plate. The circuit can also easily achieve excellent characteristics at both MZIs simultaneously, and can bring about a reduction in costs. A delay circuit (1) for PLC type demodulation has a planar lightwave circuit (1A), which is on a single PLC chip (1B) and which demodulates an optical signal which has undergone DQPSK modulation, and is provided with: an optical branching device (3) which branches the optical signal (DQPSK signal) which has undergone DQPSK modulation into two; and first and second MZIs (4, 5) which delay each of the branched DQPSK signals by 1 bit, and interfere with the signals. The delay circuit also has a wavelength plate (47) which is arranged at a central point between a first and a second arm waveguide (8, 9) of a first MZI (4), and a first and a second arm waveguide (12, 13) of a second MZI (5) so as to intersect with all the four arm waveguides (8, 9, 12, 13), with the four arm waveguides being in close proximity to the part where the wavelength plate (47) is provided.</p>
申请公布号 WO2011122539(A1) 申请公布日期 2011.10.06
申请号 WO2011JP57578 申请日期 2011.03.28
申请人 FURUKAWA ELECTRIC CO.,LTD.;KAWASHIMA, HIROSHI;NARA, KAZUTAKA 发明人 KAWASHIMA, HIROSHI;NARA, KAZUTAKA
分类号 G02B6/122;G02F2/00;H04B10/67 主分类号 G02B6/122
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