| 摘要 |
<p>Disclosed is a lateral field effect transistor which has improved switching speed and is reduced in operational failure. Specifically, a gate wiring line (43) comprises a base portion (44), a plurality of finger-like portions (45) that protrude from the base portion (44), and connecting portions (47) that respectively connect front end portions (46) of adjacent finger-like portions (45). The finger-like portions (45) of the gate wiring line (43) are respectively arranged between finger-like portions (25) of a source wiring line (23) and finger-like portions (35) of a drain wiring line (33). The base portion (44) of the gate wiring line (43) is arranged between a base portion (24) of the source wiring line (23) and the finger-like portions (35) of the drain wiring line (33), and intersects with the finger-like portions (25) of the source wiring line (23) with an insulating film interposed therebetween.</p> |
