发明名称 HIGH EFFICIENCY AMPLIFIER WITH REDUCED PARASITIC CAPACITANCE
摘要 A semiconductor amplifier is provided comprising, a substrate and one or more unit amplifying cells (UACs) formed on the substrate, wherein each UAC is laterally surrounded by a first lateral dielectric filled trench (DFT) isolation wall extending at least to the substrate and multiple UACs are surrounded by a second lateral DFT isolation wall of similar depth outside the first isolation walls, and further semiconductor regions lying between the first isolation walls when two or more unit cells are present, and/or lying between the first and second isolation walls, are electrically floating with respect to the substrate. This reduces the parasitic capacitance of the amplifying cells and improves the power added efficiency. Excessive leakage between buried layer contacts when using high resistivity substrates is avoided by providing a further semiconductor layer of intermediate doping between the substrate and the buried layer contacts.
申请公布号 US2011241159(A1) 申请公布日期 2011.10.06
申请号 US201113159635 申请日期 2011.06.14
申请人 FREESCALE SEMICONDUCTOR, INC. 发明人 ZUPAC DRAGAN;GRIESBACH BRIAN D.;KELLER THERESA M.;KEYS JOEL M.;WIPF SANDRA J.;YU EVAN F.
分类号 H01L23/58 主分类号 H01L23/58
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