发明名称 Semiconductor integrated circuit device comprising different level interconnection layers connected by conductor layers including conductor layer for redundancy
摘要 A third interconnection layer is disposed near a first interconnection layer and a second interconnection layer disposed above the first interconnection layer. The first interconnection layer and second interconnection layer are connected to each other by a regular via plug and a via plug for redundancy. The via plug for redundancy is disposed by the side of the regular via plug and between the regular via plug and the third interconnection layer. An extended portion of the second interconnection layer is extended from a portion connected to the via plug for redundancy on the second interconnection layer toward the third interconnection layer. The extended portion has a dimension smaller than the minimum dimension prescribed in the interconnection line design rule.
申请公布号 US8030773(B2) 申请公布日期 2011.10.04
申请号 US20070752999 申请日期 2007.05.24
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 KURATA NOBUHIKO;INOUE KOUICHIROU;FUJII SHINJI;MAENO MUNEAKI
分类号 H01L23/48;H01L23/52;H01L29/40 主分类号 H01L23/48
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