发明名称 Memory calibration method and apparatus for power reduction during flash operation
摘要 A method for providing reduced power consumption in a computer memory system is provided. The method includes calibrating, by a processor, a volatile memory of the computer memory system at a first and a second operating speed, where the second operating speed is higher than the first operating speed. The method also includes operating, by a memory controller coupled to the processor and the volatile memory, the volatile memory at the second operating speed if a main power source provides power to the computer memory system. The method further includes operating, by the memory controller, the volatile memory at the first operating speed if a backup power source provides power to the memory controller and the volatile memory. The backup power source provides power to the memory controller and the volatile memory when there is a loss of main power to the computer memory system.
申请公布号 US2011239021(A1) 申请公布日期 2011.09.29
申请号 US201113012299 申请日期 2011.01.24
申请人 DOT HILL SYSTEMS CORPORATION 发明人 VEDDER REX WELDON;GOLSON BRADFORD EDWIN;PETERS MICHAEL JOSEPH
分类号 G06F1/32 主分类号 G06F1/32
代理机构 代理人
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