发明名称 LOW POWER MEMORY ARRAY COLUMN REDUNDANCY MECHANISM
摘要 A low power memory array column redundancy mechanism includes a memory unit having a memory array and a multiplexer unit. The memory array includes a plurality of columns, which includes a plurality of data columns and one or more unused columns. The multiplexer unit may selectively provide a constant value to the one or more unused columns of the memory array, and provide write data to the plurality of data columns during each write operation of the plurality of columns.
申请公布号 US2011235447(A1) 申请公布日期 2011.09.29
申请号 US20100729489 申请日期 2010.03.23
申请人 HESS GREG M 发明人 HESS GREG M.
分类号 G11C29/00 主分类号 G11C29/00
代理机构 代理人
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