发明名称
摘要 A method of fabricating a plurality of chips, with each chip including at least one circuit. This method includes the successive steps of creating chips on a layer of semiconductor material that is integral with a substrate; forming a weakening pattern corresponding to a predetermined cutting pattern on a support; transferring the chip-containing layer from the substrate to the support; and forming individual chips by cutting the chip-containing layer in accordance with the predetermined cutting pattern. Also, an assembly for fabricating a plurality of chips, each chip including at least one circuit provided on a layer of semiconductor material that is carried by a support that includes a weakening pattern corresponding to a predetermined cutting pattern for forming individual chips, with the support being obtained by assembling a plurality of individual tiles with boundaries between the individual tiles corresponding to the weakening pattern. The tiles may be assembled by disposing a binder between the individual tiles, with the binder ensuring temporary bonding of the tiles.
申请公布号 JP4782107(B2) 申请公布日期 2011.09.28
申请号 JP20070510073 申请日期 2005.04.25
申请人 发明人
分类号 H01L21/301;H01L21/68;H01L21/78 主分类号 H01L21/301
代理机构 代理人
主权项
地址