发明名称 |
Multiple-core processor supporting multiple instruction set architectures |
摘要 |
Multiple instruction set architectures are supported in a system that provides a power-efficient and flexible platform for virtual machine environments requiring multiple support for multiple instruction set architectures (ISAs). A processor includes multiple cores having disparate native ISAs and that may be selectively enabled for operation, so that power is conserved when support for a particular ISA is not required of the processor. A hypervisor controls operation of the cores, locates a core and enables it if necessary when a request to instantiate a virtual machine having a specified ISA is received. The ISA may be specified by a particular operating system and/or application program requirements.
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申请公布号 |
US8028290(B2) |
申请公布日期 |
2011.09.27 |
申请号 |
US20060468547 |
申请日期 |
2006.08.30 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
RYMARCZYK JAMES WALTER;IGNATOWSKI MICHAEL;HELLER, JR. THOMAS J. |
分类号 |
G06F9/46;G06F15/00;G06F15/76 |
主分类号 |
G06F9/46 |
代理机构 |
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代理人 |
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地址 |
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