发明名称 OUTPUT BUFFER
摘要 PROBLEM TO BE SOLVED: To reduce power consumption while ensuring the amplitude of an output signal of an output buffer. SOLUTION: A clamp transistor M3 is inserted in series between a P-channel field effect transistor M1 and an N-channel field effect transistor M2, and an intermediate level between a high potential supplied to a source of the P-channel field effect transistor M1 and a low potential supplied to a source of the N-channel field effect transistor M2 is inputted into a gate of the clamp transistor M3, thereby clamping a drain potential of the N-channel field effect transistor M2. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2011188013(A) 申请公布日期 2011.09.22
申请号 JP20100047858 申请日期 2010.03.04
申请人 TOSHIBA CORP 发明人 SHIMIZU ARITAKE
分类号 H03K19/0175 主分类号 H03K19/0175
代理机构 代理人
主权项
地址