发明名称 Data processing device with low-power cache access mode
摘要 A processor can operate in three different modes. In an active mode, a first voltage is provided to the processor, where the first voltage is sufficient to allow the processor to execute instructions. In a low-power mode, a retention voltage is provided to the processor. The processor consumes less power in the retention mode than in the active mode. In addition, the processor can operate in a third mode, where a voltage is provided to the processor sufficient to allow the processor to process cache messages, such as coherency messages, but not execute other normal operations or perform normal operations at a very low speed relative to their performance in the active mode.
申请公布号 GB2460602(B) 申请公布日期 2011.09.21
申请号 GB20090018043 申请日期 2008.05.02
申请人 ADVANCED MICRO DEVICES, INC 发明人 ALEX BRANOVER;FRANK P HELMS;MAURICE BENNET STEINMAN
分类号 G06F1/32 主分类号 G06F1/32
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