| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which interference between adjoining cells can be reduced and the expansion of a chip area can be suppressed. <P>SOLUTION: In a memory cell array 1, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are disposed in a matrix form. Sense amplifiers are connected to the bit lines, respectively. A control circuit 7 controls voltages of the word lines and the bit lines, and writes data into the memory cells or reads data from the memory cells. First and fourth selection transistors BLS1 and BLS4 are provided between the first and fourth bit lines BL1, BL4 and the first sense amplifier, and connect the first and fourth bit lines to the first sense amplifier 2a; and second and third selection transistors BLS2 and BLS3 are provided between the second and third bit lines BL2, BL3 and the second sense amplifier, and connect the second and third bit lines to the second sense amplifier. <P>COPYRIGHT: (C)2011,JPO&INPIT</p> |
