发明名称 |
Multiple voltage threshold timing analysis for a digital integrated circuit |
摘要 |
An approach for performing multiple voltage threshold timing analysis for a digital integrated circuit is described. In one embodiment, there is a multiple voltage threshold timing analysis tool for performing a multiple voltage threshold timing analysis of a digital integrated circuit having at least one logic gate loaded by an interconnect circuit. In this embodiment, a characterization data retrieving component is configured to obtain characterization data describing driving behavior of the at least one logic gate. An interconnect circuit model retrieving component is configured to obtain a model of the interconnect circuit. A multiple voltage threshold timing analysis component is configured to derive a sequence of crossing times for the driving point voltage waveform to advance between successive voltage thresholds. The multiple voltage threshold timing analysis component also generates a voltage waveform from the derived sequence of crossing times.
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申请公布号 |
US8020129(B2) |
申请公布日期 |
2011.09.13 |
申请号 |
US20080021723 |
申请日期 |
2008.01.29 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
ABBASPOUR SOROUSH;FELDMANN PETER |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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