发明名称 Layout method and layout apparatus for semiconductor integrated circuit
摘要 In a layout method for a semiconductor integrated circuit by using cell library data, a plurality of cell patterns are arranged in a first direction. One of gate patterns in one of the plurality of cell patterns is specified as a reference gate pattern. An additional cell pattern is arranged in a second direction orthogonal to the first direction such that a number of gate patterns within a predetermined area containing the reference gate pattern satisfies a constraint condition.
申请公布号 US8020121(B2) 申请公布日期 2011.09.13
申请号 US20080230629 申请日期 2008.09.02
申请人 RENESAS ELECTRONICS CORPORATION 发明人 KOBAYASHI NAOHIRO
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项
地址