| 摘要 |
Digital broadband phased antenna array (DBPAA) includes M channels of reception, each of those includes a connected in series antenna element, channel amplifier, and M channel quantizer, analog multiplexer of channels, analog-digital transformer (ADT) of sampled signal, synthesizer of reference frequencies and addresses, exchange channel, ray processor that includes M buffer receiving shift registers, arithmetical device, controller of ray processor that includes generator of syhchro-pulses address generator, coder of integer quantization. To the controller of processor of rays permanent memory (PM) is included, for codes of the closest-accuracy stabilization, decoder of code of accurate stabilization is connected with input connected to the output of the lower registers sof PM codes of approximate-accurate stabilization and withj outputs – to the bus “selection of crystal”. To the ray processor M channel selectors “reception-reading” of digital signals inputs are included of which “frequency of selection” (F.Sel), input date (F. Obm.)", "Input data", "Adr. " are connected to similar inputs of the exchange channel. Arithmetical device of the processor of rays includes m table digital phasing filters that includem devices of flash-memory, address serial inputs of those are combined and connected to the output of respective channel multiplexer, at that the inputs “C” are combined and connected to the output F2 of generator of synchro-signals, inputs “Zchyt” are combined and connected to the output F3 of generator of synchro-signals, inputj of each device of flash memory is connected to one ofm outputs “Cryst. Selection” of controller of ray processor, outputs of the devices of the flash-memory are combined and are output of digital phasing filter, parallel m input adder that includes m-1 two-input parallel adders, at that the first and the second inputs of the first adder are connected to the outputs of the first and the second phasing filters, respectively, second inputs of the other m two-input parallel adders are connected to the outputs of the other m-2 phasing filters, first inputs of the m-2 two-input parallel adders, beginning from the second one, are connected to the output of the previous adder, and the output of the (m-1)-th two input parallel adder is output of the digital broadband FAR and the channel amplifier of each receiving channel is arranged as connected in series high frequency amplifier (HF), pre-selector, mixer, filter of intermediate frequency (IF), amplifier of IF, and heterodyne input of the mixer is connected to heterodyne inputs of the mixer of channel amplifiers of the other receiving channels and connected to the output “heterodyne frequency (H.F)” of synthesizer of reference frequencies and addresses. |
