发明名称 ARCHITECTURE DE REGISTRE MEMOIRE A DETECTION D'ERREUR INTEGRE ET PROCEDE DE DETECTION D'ERREUR ASSOCIE
摘要 <p>The architecture has memory elements provided for storing data bits (Qi) introduced as script. An additional memory element is provided in a row (Lj) for storing a bit of a row part calculated on data bits associated with the row. Another additional memory element is provided in a column (Ck) for storing a bit of a column part calculated on data bits associated to the column. An error correction unit receives a row part error signal (ErrLj) and a column part error signal (ErrCk) associated to the data bits. Independent claims are also included for the following: (1) a method for testing a memory register (2) a method for detecting an error in a memory register.</p>
申请公布号 FR2920894(B1) 申请公布日期 2011.09.09
申请号 FR20070006355 申请日期 2007.09.11
申请人 THALES 发明人 DERVIN PATRICK
分类号 G06F11/10 主分类号 G06F11/10
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