Reconfigurable processor architecture

摘要

We propose a reconfigurable data processor architecture (1). Said processor architecture comprises: a first plurality of data processing elements (3; 3.1, 3.2,...), each of said first plurality of data processing elements comprising a respective synchronization unit, a data link structure (4) adapted for dynamically interconnecting a number of said data processing elements, at least one configuration register, and, preferably, at least one control unit (7) in operative connection with said configuration register for controlling a contents thereof, wherein, based on the contents of said configuration register, said first plurality of data processing elements (3; 3.1, 3.2,...) is adapted for temporarily constituting at runtime at least one group (2) of one or more of said data processing elements from said first plurality of data processing elements dynamically via said data link structure, wherein said synchronization units are adapted for synchronizing data processing by individual data processing elements within said group of data processing elements. Said first plurality of data processing elements may be reconfigurably grouped and thus adapted to various data processing tasks at runtime. In this way, data processing efficiency may be greatly increased.