Multithreaded processor with interleaved instruction pipelines

摘要

A multithreaded processor comprising means for controlling a plurality of threads, including means for storing data; means for fetching instructions for one of the plurality of threads from the means for storing data; means for decoding instructions fetched; and means for executing the instructions decoded, including means for interleaved multithreaded instruction pipelining; wherein the means for executing the instructions decoded independently execute the instructions decoded for the one of the plurality of threads.