发明名称 Cache system
摘要 <p>A cache system includes a primary cache memory configured to input and output data between a computation unit, the primary cache memory includes multi-port memory units each including a storing unit that stores unit data having a first data size, a writing unit that simultaneously writes sequentially inputted plural unit data to consecutive locations of the storing unit, and an outputting unit that reads out and outputs unit data written in the storing unit, wherein when writing data having a second data size that is an arbitrary multiple of a first data size and is segmented into unit data to the primary cache memory, the data is stored in different multi-port memory units by writing the sequential unit data to a subset of the multi-port memory units, and writing the other sequential unit data to another subset of the multi-port memory units.</p>
申请公布号 EP2354954(A1) 申请公布日期 2011.08.10
申请号 EP20110153588 申请日期 2011.02.07
申请人 FUJITSU LIMITED 发明人 HIRANO, TAKAHITO
分类号 G06F12/08 主分类号 G06F12/08
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