发明名称 PARALLEL SIGNAL PROCESSING PROCESSOR
摘要 <p><P>PROBLEM TO BE SOLVED: To prevent deterioration of the use efficiency of an instruction memory by storing different programs in an instruction memory in each SIMD(Single Instruction Multiple Data) arithmetic unit. <P>SOLUTION: Each of SIMD arithmetic units 1-1 to 1-3 includes an instruction fetch control part 12 for, when an instruction memory shown by a decoder selection signal is a self-instruction memory 11, acquiring an SIMD program stored in the self-instruction memory 11, and for applying the SIMD program to the other SIMD arithmetic unit 1, and for, when the instruction memory shown by the decoder selection signal is not the self-instruction memory 11, acquiring the SIMD program from the other SIMD arithmetic unit 1. <P>COPYRIGHT: (C)2011,JPO&INPIT</p>
申请公布号 JP2011145759(A) 申请公布日期 2011.07.28
申请号 JP20100004055 申请日期 2010.01.12
申请人 MITSUBISHI ELECTRIC CORP 发明人 HATTORI SHINICHI
分类号 G06F15/80 主分类号 G06F15/80
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