| 摘要 |
A single pulse shaper with pulses of fixed length equal to one clock cycle, with adjustable delay comprises a reversible binary countdown counter having clock input, integrating/countdown set input, synchronous parallel load enable input, loading data inputs, computing enable input, asynchronous reset input, overflow input, first and second elements OR, an inverter, a circuit comprising in series connected a resistor and a capacitor, a start/stop device comprising synchronous flip-flop having asynchronous reset input, first and second two-input elements AND. JK-trigger having asynchronous reset input, a third two-input element AND are incorporated, output of the third two-input element AND serves as output of the shaper. |
