摘要 |
In one embodiment, the present invention includes a system-on-a-chip (SoC) with first and second cores, interface logic coupled to the cores, chipset logic coupled to the interface logic, and a virtual firewall logic coupled between the chipset logic and the second core. The interface logic may include a firewall logic, a bus logic, and a test logic, and the chipset logic may include a memory controller to provide for communication with a memory coupled to the SoC. In some system implementations, both during test operations and functional operations, the second core can be disabled during normal operation to provide for a single core SoC, enabling greater flexibility of use of the SoC in many different implementations. Other embodiments are described and claimed. |
申请人 |
INTEL CORPORATION |
发明人 |
RACHAKONDA, RAMANA;HACKING, LANCE E.;REDDY, MAHESH K.;BORGER, LORI R.;TEH, CHEE HAK;BHATIA, PAWITTER P.;LEE, JOHN P. |