FUNCTIONAL STRUCTURE OF PRE-ADDER f([mj]&[mj,0]) OF PARALLEL-SERIES MULTIPLIER f() WITH PROCEDURE FOR LOGIC DIFFERENTIATION d/dn OF FIRST INTERMEDIATE SUM [S1Çè]f(})- OR STRUCTURE OF ACTIVE ARGUMENTS OF MULTIPLICAND [0,mj]f(2n) and [mj,0]f(2n) (VERSIONS)

摘要

FIELD: information technology. ^ SUBSTANCE: in one version of the invention, the functional structure in each bit contains elements executing logic functions OR, AND, NAND and NOR, wherein each bit is in form of two summation channels for generating a positive sum and a conditionally negative sum. ^ EFFECT: faster pre-summation process of a multiplicand in parallel-serial multiplier. ^ 4 cl