发明名称 Simulation circuit of PCI express endpoint and downstream port for a PCI express switch
摘要 Single hardware subsystems that present two software views that appear to be two separate hardware subsystems attached in a hierarchy are implemented with PCI arrangements. In an embodiment, a hardware arrangement is configured to emulate two virtually separate hierarchical subsystems in a single hardware block. This emulation facilitates the coupling of devices to PCI Express communications links while addressing PCI-Express linking requirements for such devices.
申请公布号 US7983888(B2) 申请公布日期 2011.07.19
申请号 US20050592191 申请日期 2005.03.21
申请人 NXP B.V. 发明人 EVOY DAVID R.;ROSE JERRY MICHAEL
分类号 G06F17/50;G06F13/40 主分类号 G06F17/50
代理机构 代理人
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