发明名称 |
Macro-block level parallel video decoder |
摘要 |
A macro-block level parallel video decoder for a parallel processing environment is provided. The video decoder includes a Variable Length Decoding (VLD) block for decoding the encoded Discrete Cosine Transform (DCT) coefficients, a master node that receives the decoded DCT coefficients, and multiple slave nodes/processors for parallel implementation of Inverse Discrete Cosine Transform (IDCT) and motion compensation at the macro-block level. Also provided is a method for macro-block level video decoding in a parallel processing system.
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申请公布号 |
US7983342(B2) |
申请公布日期 |
2011.07.19 |
申请号 |
US20050191613 |
申请日期 |
2005.07.28 |
申请人 |
STMICROELECTRONICS PVT. LTD. |
发明人 |
SAHA KAUSHIK;SARKAR ABHIK;MAITI SRIJIB NARAYAN |
分类号 |
H04N7/12;H04B1/66;H04N11/02;H04N11/04 |
主分类号 |
H04N7/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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