| 摘要 |
PURPOSE: A delay-locked-loop circuit, and a semiconductor device and a memory system including the same are provided to shorten time required for synchronizing an internal clock signal to an external clock signal in case of the change of the clock signal. CONSTITUTION: A delay-locked-loop circuit(1000) includes a first delay-locked-loop(1100) and a second delay-locked-loop(1300). The first delay-locked-loop generates a first internal clock signal, which is synchronized with an external clock signal by controlling the delayed amount of the external clock signal, when an external clock signal includes low frequency. The second delay-locked-loop generates a second internal clock signal, which is synchronized with the external clock signal by controlling the delayed amount of the external clock signal, when the external clock signal includes high frequency. |
