发明名称 FLIP-FLOP CIRCUIT AND FREQUENCY DIVIDER CIRCUIT
摘要 <p><P>PROBLEM TO BE SOLVED: To improve the maximum operating frequency by reducing power consumption in a flip-flop circuit. <P>SOLUTION: A first data holding circuit (18) of a master-side element (100) and a second data holding circuit (19) of a slave-side element (200), are constituent elements of a flip-flop circuit. The flip-flop circuit has a function for switching the ON/OFF operating state of operations of the first/second data holding circuits. The flip-flop circuit makes timing control to each of the first/second data holding circuits so as to reduce an unnecessary current, to eliminate effects of a parasitic capacitance, to operate at a low power consumption, and to have the high maximum operating frequency. <P>COPYRIGHT: (C)2011,JPO&INPIT</p>
申请公布号 JP2011135297(A) 申请公布日期 2011.07.07
申请号 JP20090292629 申请日期 2009.12.24
申请人 PANASONIC CORP 发明人 YAMAGUCHI SATOSHI
分类号 H03K3/3562;H03K3/037;H03K23/50;H03K23/66 主分类号 H03K3/3562
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