发明名称 A PACKAGE SUBSTRATE AND A METHOD OF FABRICATING THE SAME
摘要 PURPOSE: A package substrate and a manufacturing method thereof are provided to minimize stress of a chip in a build-up process. CONSTITUTION: A mold unit(112) is formed to surround a chip(111). A base part(110) includes a connection portion for connecting a chip formed within the mold unit with a terminal portion formed at an outer surface of the mold unit. A build-up layer(120) includes a lateral surface of a base unit. The build-up layer is formed on one surface of the base part having the terminal part. The build-up layer includes a circuit layer which is connected to the terminal portion.
申请公布号 KR20110075422(A) 申请公布日期 2011.07.06
申请号 KR20090131869 申请日期 2009.12.28
申请人 SAMSUNG ELECTRO-MECHANICS CO., LTD. 发明人 HONG, JU PYO;KWEON YOUNG DO;KIM, JIN GU;PARK, SEUNG WOOK;LEE, HEE KON
分类号 H01L23/10 主分类号 H01L23/10
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