发明名称 |
3D INTEGRATION OF A MIM CAPACITOR AND A RESISTOR |
摘要 |
<p>The present invention relates to an electronic component, that comprises, on a substrate, at least one integrated MIM capacitor, (114) an electrically insulating first cover layer (120) which partly or fully covers the top capacitor electrode (118) and is made of a lead-containing dielectric material, and a top barrier layer (122) on the first cover layer. The top barrier layer serves for avoiding a reduction of lead atoms comprised by the first cover layer under exposure of the first cover layer to a reducing substance. An electrically insulating second cover layer (124) on the top barrier layer has a dielectric permittivity smaller than that of the first cover layer establishes a low parasitic capacitance of the cover-layer structure. The described cover-layer structure with the intermediate top barrier layer allows to fabricate a high-accuracy resistor layer (126.1) on top.</p> |
申请公布号 |
EP2340552(A1) |
申请公布日期 |
2011.07.06 |
申请号 |
EP20090771413 |
申请日期 |
2009.10.22 |
申请人 |
NXP B.V. |
发明人 |
ROEST, AARNOUD, LAURENS;KLEE, MAREIKE;MAUCZOK, RUDIGER, GUNTER;VAN LEUKEN-PETERS, LINDA;WOLTERS, ROBERTUS, ADRIANUS, MARIA |
分类号 |
H01L21/02;H01L23/522;H01L27/02;H01L27/06 |
主分类号 |
H01L21/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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