| 摘要 |
Error correction code (ECC) decoding architecture design using synthesis-time design parameters. An approach is presented herein by which an ECC decoding architecture can be designed using synthesis-time design parameters. The manner presented herein allows for a designer to arrive at an ECC decoding architecture in a more direct, straightforward manner that using prior art means. A number of considerations (e.g., architecture parameters, semi-soft design constraints, parallel implementation, etc.) are initially provided; certain or all of these considerations can be predetermined, determined adaptively, and/or modified during the design process. A designer is provided a means by which a most desirable ECC decoding architecture can be arrived at relatively quickly.
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