An input signal DT contains a segment synchronization signal based on the ATSC standard. A clock doubling block (111) doubles a clock CK. A selector type sampling block (112) selects a sampling point among a plurality of timings defined by the doubled clock and samples the input signal DT at the selected sample point. Moreover, the selector type sampling block (112) switches the sampling point from one to another while synchronization is not established. After the segment synchronization is established, a synchronization detection apparatus may maintain the synchronization established state until the field synchronization detection fails and may shift the synchronization detection signal in the temporal direction in accordance with the bit error rate RT when outputting the signal.
