SIGNAL RECEIVING CIRCUIT, MEMORY CONTROLLER, PROCESSOR, COMPUTER, AND PHASE CONTROL METHOD

摘要

Disclosed is a signal receiving circuit (2) that receives a signal from a memory module (4) or other signal source, the signal receiving circuit (2) comprising a phase detection unit (10) and a latency control unit (12). The phase detection unit (10) detects the phase difference between the received signal and a clock signal. The latency control unit (12) further comprises a first latency unit (a phase latency unit (16)) and a second latency unit (a phase latency unit (18)). The first latency unit receives the detected phase difference, and introduces latency into the phase of the received signal within a range not exceeding a degree of latency designated in units of a prescribed phase difference. If the phase difference exceeds the prescribed phase difference, the second latency unit changes the degree of latency of the received signal, designated in units of the prescribed phase difference.